This invention relates to acquisition of high frequency analog signals.
A high speed FISO (fast in, slow out) acquisition system is described in U.S. Pat. No. 4,271,488 to Saxe. FIG. 1 of this prior art patent teaches and shows a memory array 10 in which sample and hold elements 12 are used to sample an analog signal from an analog bus 14. Each sample and hold element is selected by digital command from an X shift register 22 and a Y shift register 24. The acquisition system enables sampling to be performed at a relatively high rate, but the maximum rate is limited by the clock rate at which data is shifted through the X and Y shift registers. The maximum rate is thus a function of the complexity of the shift register design and the delay of the elements used in that design. Due to the ever increasing demands for higher and higher sampling rates, the limitation imposed by the X and Y shift registers is no longer acceptable. What is desired is an analog acquisition system that is not limited by the maximum clock rate of a shift register.